#18.. jeps, det vil det.. Intel bruger alt for mange "stages" hvis du spørger mig..
et, det giver varme..
to, kan forklares sådan:
This increase in pipeline stages means that the number of clock cycles for data and instructions to reach the core has increased from 20 clock cycles to 31 cycles. In general, if nothing goes wrong, there is very little difference between a long and a short pipeline, however, if the wrong data have been predicted and are speculatively preloaded into the pipeline, these data have to be processed along the entire length of the pipeline as well before they can be evicted at the back-end. This naturally causes a bubble or delay and the size of the bubble or delay increases with the length of the pipeline.