xzipet
#0
Som skrevet står, hvad hedder det der hvor man skifter mellem 1T og 2T på sådan en DFI bræt.
Er ved at få grå hår af dette bræt.
xzipet
Er ved at få grå hår af dette bræt.
xzipet
#1
hehe..
Under ram settings er der øverst divider, næste står til "auto" sæt den til enabled - så er den fikset ;)
Under ram settings er der øverst divider, næste står til "auto" sæt den til enabled - så er den fikset ;)
#2
#1
Tak for det, tro sku heller jeg må finde mig et andet bræt. Bliver sku for hurtigt gammel af denne DFI bios.
xzipet
Tak for det, tro sku heller jeg må finde mig et andet bræt. Bliver sku for hurtigt gammel af denne DFI bios.
xzipet
#3
MSI SLI platinum... alt oc/timing-relateret er samlet i "Cell-Menu".
Desuden yder boardet bedre end dfi'et ved stock indstillinger, men der er nu ikke noget som slå dfi mht massivt oc.
Desuden yder boardet bedre end dfi'et ved stock indstillinger, men der er nu ikke noget som slå dfi mht massivt oc.
#4
Inden du nu får solgt det lækre board:
http://www.dfi-street.com/foru...
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
Har hjulpet mig meget
Mvh
Søren
http://www.dfi-street.com/foru...
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
Har hjulpet mig meget
Mvh
Søren
#5
#4 en god guide, men jeg lagde mærke til en enkelt ting omkring CAS latency, som de har taget fra lostcircuits. Det de har pastet fra lostcircuits indeholder IKKE den nyeste information om DDR SDRAM - ellers havde der stået at tRCD er den vigtigste timing i DDR SDRAM. CAS 2 eller 2.5 latency kan skjules i DDR SDRAM tilfældet, og derfor bliver CAS mindre betydningsfuld for performance. I gamle dage med SDRAM var CAS den vigtigste, men ved introduktionen af DDR SDRAM, blev det ændret.
Mvh. Uffe
Quote:
"With DDR, the situation is similar since the critical factor is not the number of words but the trashing of information in the output buffers. In clear text, this means that the read command can be issued early, that is exactly one CAS latency before the end of the burst without trashing the data in the output buffers. This, however, also means that the only difference between a CAS-2.5 and a CAS-2 part in DDR is 1/2 additional penalty cycle on a random access, whereas in in-page accesses, there is no additional penalty since the extra 1/2 clock latency is hidden behind the early command.
To reiterate, in an SDRAM situation, the additional latency of a CAS-3 part cannot be hidden, even in page hit situations, in a DDR scenario, there is no real impact of CAS-2 vs. CAS 2.5 while staying in page. Staying in page with DDR, however, underlies somewhat different rules with than with SDRAM but we'll get there shortly."
Mvh. Uffe
Quote:
"With DDR, the situation is similar since the critical factor is not the number of words but the trashing of information in the output buffers. In clear text, this means that the read command can be issued early, that is exactly one CAS latency before the end of the burst without trashing the data in the output buffers. This, however, also means that the only difference between a CAS-2.5 and a CAS-2 part in DDR is 1/2 additional penalty cycle on a random access, whereas in in-page accesses, there is no additional penalty since the extra 1/2 clock latency is hidden behind the early command.
To reiterate, in an SDRAM situation, the additional latency of a CAS-3 part cannot be hidden, even in page hit situations, in a DDR scenario, there is no real impact of CAS-2 vs. CAS 2.5 while staying in page. Staying in page with DDR, however, underlies somewhat different rules with than with SDRAM but we'll get there shortly."