Yonah

Intels nye 65nm dual core Pentium M processor, som går under kodenavnet "Yonah" kommer i 4 forskellige udgaver når den bliver lanceret næste år:

"Roadmap Intel's 65nm dual-core Pentium M successor, codenamed 'Yonah', will ship at 1.67, 1.84, 2.0 and 2.17GHz when it debuts early next year, the latest company roadmaps to be made public reveal.

The four dual-core incarnations will be accompanied by just one 2MB L2 single-core version of the part, as Intel had already announced, clocked at 1.67GHz.
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That part looks set to follow standard single-core Pentium M nomenclature, shipping as the 756 alongside today's 740, 750, 760,770 and now 780, all of which will continue to be made available through Q1 2006, according to roadmap details posted by Japanese website PCWatch.

The dual-core Yonahs will, like the dual-core Pentium D, take on a new model number series, as yet undetermined - or, at least, not mentioned on the roadmap - with the first four chips set as the x20, x30, x40 and x50.

Q1 2006 will also see the arrival of the x38 and x48, dual-core low-voltage parts, clocked at 1.50 and 1.67GHz, respectively. Come Q3 2006, and Intel will introduce the 1.84GHz x58, alongside the 2.34GHz x60, and the 1.84GHz 766, the latter based on the single-core Yonah.

Stepping back a quarter, in Q2 2006, a 1MB L2 version of the single-core Yonah will take the Celeron M family into the 65nm era with the 420, followed by the 430 and 410 mid-way through Q3. Clock speeds are not known, but it looks like they will supersede the old 3xx series chips at the same time.

Q2 looks likely to see the debut of dual-core ultra-low voltage dual-core Yonahs, at 1.06 and 1.20GHz, along with the single-core ULV Celeron M 423 - again, its clock frequency is not known.

The speeds and feeds of 'Merom', Yonah's successor aren't clear either, but the roadmap suggests a late Q3/early Q4 introduction.

Yonah will bring support for Intel's Virtualisation and Advanced Management technologies to the Centrino platform, not to mention SSE 3 support and a new power management system, dubbed Dynamic Power Co-ordination, which synchronises the two cores' individual Enhanced SpeedStep power-saving technologies. ®"

http://www.theregister.co.uk/2005/08/08/intel_mobile_roadmap/